Method for rapid estimation of wire delays and capacitances based on placement of cells
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United States of America Patent
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Aug 16, 2005
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N/A
app pub date -
May 12, 2000
filing date -
May 12, 2000
priority date (Note) -
Expired
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Abstract
A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.
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