Timing method and apparatus for integrated circuit device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 23, 2005
Grant Date -
N/A
app pub date -
Oct 31, 2002
filing date -
Oct 31, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
According to one embodiment, a timing circuit (300) can include a first control circuit (302), a first clocked circuit (304), a second clocked circuit (306), and a second control circuit (314). A first control circuit (302) may compensate for a first timing signal FCLK making a transition earlier in time than a second timing signal RCLK. A second control circuit (314) may compensate for a second timing signal RCLK making a transition earlier in time than a first timing signal FCLK. A first timing signal FCLK can be a periodic signal generated by a first PLL type circuit (310) in response to a falling edge of an external clock signal EXT CLK. A second timing signal RCLK can be a periodic signal generated by a second PLL type circuit (312) in response to a rising edge of an external clock signal EXT CLK.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully