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Abstract

A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is provided. The system has a sense amplifier, a multiplexer, delay elements, and a provision for hardwiring fast and slow circuits during packaging of a memory circuit. The sense amplifier firing path is split into a slow and a fast path and the multiplexer can select either the slow path or fast path. The memory circuit is tested after fabrication to assess whether each memory cell can be identified as slow or fast circuits and accordingly the fast path or slow path is selected by the multiplexer. The path for each memory cell may be then hardwired during packaging by connecting a select input of multiplexer to a VDD signal or a ground signal.

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