Controlling access to multiple memory zones in an isolated execution environment
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United States of America Patent
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Aug 23, 2005
Grant Date -
Apr 22, 2004
app pub date -
Oct 10, 2003
filing date -
Mar 31, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention provides a method, apparatus, and system for controlling memory accesses to multiple memory zones in an isolated execution environment. A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.
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