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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
TRU-SI TECHNOLOGIES INC	657 N PASTORIA AVENUE SUNNYVALE CA 94085

International Classification(s)

• B65H:HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS....

• [Classification Symbol]

• [Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Berger, Alexander J	Palo Alto, CA	15	204
Kretz, Frank E	Santa Clara, CA	11	147

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
August 30, 2005	US,6935830,B2   US6935830B2	GRANTED PATENT AS SECOND PUBLICATION
January 16, 2003	US,20030014158,A1   US20030014158A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 6935830

Alignment of semiconductor wafers and other articles

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