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Abstract

A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate a wide range of operating frequencies. A clock signal synchronized with an input clock signal propagated through an input time delay and an output time delay is generated by delaying an input buffered clock signal by a first time delay based on the frequency of the input buffered clock signal, and further delaying the delayed input buffered clock signal by a second time delay to compensate for timing skew introduced by the input time delay, the output time delay and the process of delaying the input buffered clock signal.

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First Claim