Wafer scale package and method of assembly
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United States of America Patent
Stats
-
Sep 6, 2005
Issued Date -
N/A
app pub date -
Apr 9, 2004
filing date -
Mar 26, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
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