Interconnection network for a field programmable gate array
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United States of America Patent
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-
Sep 6, 2005
Grant Date -
Aug 5, 2004
app pub date -
Jan 23, 2004
filing date -
Aug 4, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.
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