Systems and methods for memory read response latency detection
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United States of America Patent
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Sep 6, 2005
Grant Date -
N/A
app pub date -
May 22, 2002
filing date -
May 22, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for determining a memory read latency includes a memory, a memory read circuit, and a latency detector. An identifiable pattern of data is written to at least one location in the memory, and a read request and the address of the identified pattern are sent to the memory. The latency detector determines a read latency period based on detecting the identifiable pattern of data.
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