Test methodology for direct interconnect with multiple fan-outs
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United States of America Patent
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Sep 13, 2005
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N/A
app pub date -
Mar 27, 2003
filing date -
Mar 27, 2003
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Abstract
A test cell and method of operation are disclosed. The test cell may be cascaded with other test cells to form a test structure that spans across any number of slices and/or tiles in a programmable logic device. The test structure behaves like a register, and may be used to test direct interconnects and any number their fan-out lines simultaneously.
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