Phase error cancellation circuit and method for fractional frequency dividers and circuits incorporating same
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United States of America Patent
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Sep 13, 2005
Grant Date -
Nov 27, 2003
app pub date -
Mar 28, 2003
filing date -
Mar 28, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A frequency divider circuit (11) has an input port for an input signal (Fo) to be divided, an output port for a divided signal (FDIV), and means (12-19) for providing a variable division-ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residual quantization error signal (R) are dithered.
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