Stacked semiconductor package with circuit side polymer layer
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United States of America Patent
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Sep 27, 2005
Grant Date -
Sep 2, 2004
app pub date -
Mar 4, 2004
filing date -
Jul 10, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
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