Method for using a hard mask for critical dimension growth containment

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United States of America Patent

PATENT NO 6951820
APP PUB NO 20020132485A1
SERIAL NO

10045318

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

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Patent Owner(s)

  • SILICON VALLEY BANK;SPTS TECHNOLOGIES LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cofer, Alferd Petaluma, CA 17 247
DeOrnellas, Stephen P Santa Rosa, CA 24 291
Jerde, Leslie G Novato, CA 17 242

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