System with dual rail regulated locked loop
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United States of America Patent
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-
Oct 4, 2005
Grant Date -
Sep 25, 2003
app pub date -
Feb 25, 2003
filing date -
Mar 22, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.
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