Function block architecture for gate array and method for forming an asic

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United States of America Patent

PATENT NO 6954917
SERIAL NO

10460343

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Abstract

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A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place and route layout of the circuit design which leaves a group of buffer modules unused, based upon a partially predesigned integrated circuit, in which the partially predesigned integrated circuit includes a plurality of logic modules and a plurality of buffer modules uniformly distributed amongst the logic modules; evaluating load and timing characteristics for the initial place and route layout of the circuit design; and integrating buffer modules from the group of unused buffer modules into the circuit design, based on the load and timing characteristics evaluated. A gate array, for forming the application specific integrated circuit in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers.

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Patent Owner(s)

Patent OwnerAddress
HANGER SOLUTIONS LLC44 MILTON AVENUE SUITE 254 ALPHARETTA GA 30009

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gamal, Abbas El Palo Alto, CA 13 690
How, Dana Palo Alto, CA 44 475
Srinivasan, Adi Fremont, CA 27 631

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