Hardware supported software pipelined loop prologue optimization
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United States of America Patent
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Oct 11, 2005
Grant Date -
Sep 19, 2002
app pub date -
Oct 4, 2001
filing date -
Feb 17, 1999
priority date (Note) -
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Abstract
A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating an initiation interval time (IN) for a pipelined stage of the loop. A loop operation time latency (Tld) and a number of loop operations (Np) from the pipelined stages to peel based on IN and Tld is then determined. The loop operation is peeled Np times and copied before the loop in the software code. A vector of registers is allocated and the results of the peeled loop operations and a result of an original loop operation is assigned to the vector of registers. Memory addresses for the results of the peeled loop operations and original loop operation are also assigned.
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