Fail-safe zero delay buffer with automatic internal reference
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United States of America Patent
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Oct 18, 2005
Issued Date -
N/A
app pub date -
Apr 28, 2004
filing date -
Aug 13, 2001
priority date (Note) -
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.
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