Reduced-width low-error multiplier
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United States of America Patent
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Oct 18, 2005
Grant Date -
Mar 14, 2002
app pub date -
May 22, 2001
filing date -
Jan 31, 2001
priority date (Note) -
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Abstract
This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.
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