Method and apparatus for routing nets in an integrated circuit layout

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United States of America Patent

PATENT NO 6957408
SERIAL NO

10215563

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Abstract

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Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit ('IC') layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this method then generates a geometric route for the selected net.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldwell, Andrew Santa Clara, CA 120 1490
Jacques, Etienne Sunnyvale, CA 32 629
Teig, Steven Menlo Park, CA 333 6577

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