Gridless IC layout and method and apparatus for generating such a layout

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6957411
SERIAL NO

10229108

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Abstract

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Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit ('IC') layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies preferred non-Manhattan wiring directions. It also uses a manufacturing grid as the only grid for constraining the location of interconnect lines for connecting the net's routable elements.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC A DELAWARE CORPORATION2655 SEELY AVE BUILDING 5 MS 5B1 SAN JOSE CA 95134

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldwell, Andrew Santa Clara, CA 120 1490
Jacques, Etienne Sunnyvale, CA 32 629
Teig, Steven Menlo Park, CA 333 6577

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