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Abstract

A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal Fφ0 from a reference signal Fref A frequency accumulator (132, 152) is preloaded with a preload value PK1 and receives one reference signal cycle as a clock signal, receives a constant K1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count KMAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value PC1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C1 as an input thereto. The phase accumulator (136, 156) has a maximum count CMAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal Fref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fφ1 whose phase shift φ1 relative to F0φ is a function of PK1 and PC1.

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First Claim