Method and apparatus for cascade programming a chain of cores in an embedded environment
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United States of America Patent
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Nov 1, 2005
Grant Date -
N/A
app pub date -
Dec 18, 2001
filing date -
Dec 18, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for clearing and programming the memory of an FPGA IC, when the IC is comprised of a plurality of cores. The system clears the memory of the of cores. The system then sequentially verifies completion of clearing memory of each core. The system then provides a programming ready signal to all cores when the memory of a last core has has been cleared. The system then sends the bitstream data to a first core. After the first core is programmed, the balance of the bitstream data is sent to a next core. This process is repeated until all of the cores are programmed.
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