Single rank memory module for use in a two-rank memory module system
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United States of America Patent
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Nov 1, 2005
Grant Date -
Mar 17, 2005
app pub date -
Sep 12, 2003
filing date -
Sep 12, 2003
priority date (Note) -
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Abstract
A memory module for use in a two rank memory module system includes a plurality of memory devices and a control circuit. In one embodiment, the control circuit may be configured to generate a chip select signal that is provided to each of the memory devices. The chip select signal may be dependent upon assertions of a first bank chip select signal and a second bank chip select signal received from a memory controller. The control circuit may be further configured to generate an address signal that is provided to each of the memory devices. The address signal may be asserted dependent upon which of the first bank chip select signal and the second bank chip select signal are asserted.
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