System to perform horizontal additions
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United States of America Patent
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Nov 1, 2005
Issued Date -
N/A
app pub date -
Jul 9, 2002
filing date -
Mar 31, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method and apparatus for including in a processor instructions for performing intra-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the result of an intra-add operation on data elements in the first packed data.
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