Hard mask spacer for sublithographic bitline

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United States of America Patent

PATENT NO 6962849
SERIAL NO

10729732

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

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Patent Owner(s)

  • CYPRESS SEMICONDUCTOR CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ghandehari, Kouros Santa Clara, CA 39 635
Jamali-Beh, Taraneh Santa Cruz, CA 2 26
Kamal, Tazrien San Jose, CA 42 1018
Khathuria, Ashok M San Jose, CA 9 133
Qian, Weidong Sunnyvale, CA 17 396
Ramsbey, Mark T Sunnyvale, CA 124 2399

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