Importance

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Abstract

A self-aligned planar DMOS transistor structure is disclosed, in which a p-body diffusion region is selectively formed in an n-/n+ epitaxial silicon substrate; a self-aligned p+ contact diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sacrificial dielectric spacer; a self-aligned n+ source diffusion ring is formed in a surface portion of the p-body diffusion region through a second self-aligned implantation window formed between a protection dielectric layer and a self-aligned implantation masking layer surrounded by the sacrificial dielectric spacer; a self-aligned source contact window is formed on the self-aligned n+ source diffusion ring surrounded by a sidewall dielectric spacer and on the self-aligned p+ contact diffusion region surrounded by the self-aligned n+ source diffusion ring; and a heavily-doped polycrystalline-silicon gate layer is selectively silicided in a self-aligned manner.

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First Claim