Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocks
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United States of America Patent
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Nov 22, 2005
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N/A
app pub date -
Oct 1, 2001
filing date -
Oct 26, 2000
priority date (Note) -
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Abstract
A method for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. A synchronized clock signal is supplied to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The frequency of the clock signal can be changed dynamically depending on the analog function to be achieved.
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