Combination NAND-NOR memory device
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United States of America Patent
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Nov 22, 2005
Grant Date -
Jul 7, 2005
app pub date -
Jan 7, 2004
filing date -
Jan 7, 2004
priority date (Note) -
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Abstract
An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.
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