Natural analog or multilevel transistor DRAM-cell

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6969652
APP PUB NO 20050018501A1
SERIAL NO

10615124

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
YOULIZA GEHTS B V LIMITED LIABILITY COMPANY160 GREENTREE DRIVE SUITE 101 DOVER DE 19904

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Knoedgen, Horst Munich, DE 117 1092

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation