Systems and methods for multiprocessor scalable write barrier
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United States of America Patent
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Dec 6, 2005
Grant Date -
Oct 28, 2004
app pub date -
Apr 23, 2003
filing date -
Apr 23, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
Systems and methods providing a multiprocessor scalable write barrier to a main memory card table are described. The main memory is divided into multiple cards bit-mapped by the card table. In one aspect, an application store operation (reference) associated with one of the cards is detected. Responsive to detecting the reference, card table bit(s) that are mapped to the card are evaluated. Responsive to determining that the bit(s) have already been marked as dirty, the card table bit(s) are not again marked. This technique effectively reduces the probability of more than a single overlapping write operation to a card table cache line by two or more processors in the system.
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