Hierarchical linking module connection to access ports of embedded cores
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United States of America Patent
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Dec 13, 2005
Grant Date -
Oct 31, 2002
app pub date -
Jun 14, 2002
filing date -
Feb 18, 1998
priority date (Note) -
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Abstract
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
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