Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
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United States of America Patent
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Dec 13, 2005
Grant Date -
N/A
app pub date -
Dec 30, 1999
filing date -
Dec 30, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from ports in segments and each segment is assigned to one of the program threads. Ordering of segments within packets, and between packets from the same port, is maintained by a scheduler program thread. The scheduler program thread blocks a new assignment of the previously assigned port to a program thread until the program thread to which the port was previously assigned has indicated that it has completed the processing of the segment from that port.
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