High-performance non-volatile memory device and fabrication process
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United States of America Patent
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Dec 20, 2005
Grant Date -
N/A
app pub date -
Jun 30, 2003
filing date -
Jun 30, 2003
priority date (Note) -
Expired
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Abstract
An EEPROM device exhibiting high saturation current and low signal propagation delay and a process for fabricating the device that includes the formation of refractory metal silicide regions in the source and the drain regions and the gate electrode of an MOS transistor within an EEPROM memory cell. A floating-gate protect layer is formed over the floating-gate electrode and a relatively thick cap oxide layer is formed to overlie the floating-gate protect layer and the source and drain regions and gate electrode of the MOS transistor. A doped oxide layer is formed to overlie the cap oxide layer. The cap oxide layer is formed to a thickness sufficient to create strain in the channel region of the MOS transistor, while not having a thickness that could cause poor data retention in the EEPROM memory cell.
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