Method of controlling the operation of a digital state machine from a master controller in an IC-chip testing system
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United States of America Patent
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Dec 27, 2005
Grant Date -
N/A
app pub date -
May 19, 2004
filing date -
May 19, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An IC-chip testing system includes multiple digital state machines, and a master controller which controls the operation of those digital state machines by a particular method. In this method, the master controller first generates a command chain in which multiple commands for one particular digital state machine are concatenated together in a series. Thereafter, the master controller sends a single payload data packet embedded in a layered TCP/IP/network format, to that digital state machine. This single payload data packet includes the entire command chain. By concatenating many commands together in the command chain, the adverse effect of TCP/IP/network headers on the efficiency of transmission is overcome. In one particular transmission, efficiency is increased from 7.1% for sending a single command, to 89.4% for sending the entire command chain.
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