On-chip power-ground inductance modeling using effective self-loop-inductance
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United States of America Patent
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Dec 27, 2005
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app pub date -
Jul 30, 2002
filing date -
Jul 30, 2002
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Abstract
An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.
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