Method and apparatus for reading NAND flash memory array
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United States of America Patent
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Jan 3, 2006
Grant Date -
Apr 14, 2005
app pub date -
Oct 9, 2003
filing date -
Oct 9, 2003
priority date (Note) -
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Abstract
The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line.
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