SDRAM controller for parallel processor architecture
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United States of America Patent
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Jan 3, 2006
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N/A
app pub date -
Aug 31, 1999
filing date -
Aug 31, 1999
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Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
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