Processor and method for pre-fetching out-of-order instructions
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United States of America Patent
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Jan 3, 2006
Grant Date -
Feb 17, 2005
app pub date -
Aug 13, 2003
filing date -
Aug 13, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A processor and method for handling out-of-order instructions is provided. In one embodiment, the processor comprises instruction pre-fetch logic configured to pre-fetch instructions from memory. The processor further comprises instruction information logic configured to store information about instructions fetched from memory. The processor further comprises control logic configured to control temporary storage of the information related to a pre-fetched instruction if there is currently an active memory access and the currently pre-fetched instruction is an out-of-order instruction. The method pre-fetches the out-of-order in instruction, temporarily stores information associated with the out-of-order instruction in a storage location, and if the memory access completes without encountering a data fault, then saves the temporarily stored information and processes the pre-fetched instruction.
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