Generating a logic design
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United States of America Patent
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Jan 3, 2006
Grant Date -
Mar 6, 2003
app pub date -
Aug 29, 2001
filing date -
Aug 29, 2001
priority date (Note) -
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Abstract
A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.
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