Jitter control processor and a transceiver employing the same
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United States of America Patent
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Jan 10, 2006
Grant Date -
Jan 23, 2003
app pub date -
Apr 30, 2001
filing date -
Apr 30, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention provides a transceiver couplable to a communications network having a jitter control processor and methods of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a transmitter stage that controls a transmit signal. In one embodiment, the transmitter stage includes a transmit time error measurement system configured to generate a transmit time error signal as a function of timing synchronization associated with a communications network clock and a transceiver master clock, a transmit filter circuit configured to develop a filtered time error signal as a function of the transmit time error signal, and a stuffing control system configured to insert a stuffing control signal into the transmit signal as a function of the transmit time error signal and the filtered time error signal.
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