Methods for increasing instruction-level parallelism in microprocessors and digital system
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United States of America Patent
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Jan 17, 2006
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app pub date -
Jun 25, 1999
filing date -
Jun 26, 1998
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Abstract
Our micro-architectural method increases the performance of microprocessor and digital circuit designs by increasing the usable instruction-level parallelism during execution. The method can be applied to substantially increase the performance of processors in a broad range of instruction set architectures including CISC, RISC, and EPIC designs. Code blocks of instructions are transformed from the original instruction set architecture to be executed into a new instruction set architecture by an instruction stream transformation unit. The transformed code blocks are then cached in an instruction stream cache. The transformation process increases processor performance by substantially increasing the instruction-level parallelism available during execution.
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