US Patent No: 6,989,285
Number of patents in Portfolio can not be more than 2000
Method of fabrication of stacked semiconductor devices
Stats
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Jan 24, 2006
Issued date -
Aug 3, 2004
filing date -
10/911,862
serial no -
In Force
status
Importance
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Abstract
A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complementary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,146,308 Semiconductor package utilizing edge connected semiconductor dice | 52 | 1990 | |
| 5,291,061 Multi-chip stacked devices | 198 | 1993 | |
| 5,323,060 Multichip module having a stacked chip arrangement | 313 | 1993 | |
| 5,952,725 Stacked semiconductor devices | 98 | 1997 | |
| 6,165,815 Method of fabrication of stacked semiconductor devices | 69 | 1997 | |
| 6,337,227 Method of fabrication of stacked semiconductor devices | 18 | 2000 | |
| 6,784,023 Method of fabrication of stacked semiconductor devices | 40 | 2001 | |
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| 4,862,245 Package semiconductor chip | 513 | 1988 | |
| 5,252,857 Stacked DCA memory chips | 227 | 1991 | |
| 5,567,654 Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging | 89 | 1994 | |
| 5,466,634 Electronic modules with interconnected surface metallization layers and fabrication methods therefore | 58 | 1994 | |
| 5,786,237 Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips | 17 | 1995 | |
| 5,656,553 Method for forming a monolithic electronic module by dicing wafer stacks | 59 | 1996 | |
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| 5,012,323 Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe | 258 | 1989 | |
| 5,229,647 High density data storage using stacked wafers | 318 | 1992 | |
| 5,851,845 Process for packaging a semiconductor die using dicing and testing | 237 | 1995 | |
| 5,917,242 Combination of semiconductor interconnect | 168 | 1996 | |
| 6,380,630 Vertical surface mount package utilizing a back-to-back semiconductor device module | 12 | 2000 | |
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| 5,147,815 Method for fabricating a multichip semiconductor device having two interdigitated leadframes | 160 | 1991 | |
| 5,927,993 Backside processing method | 26 | 1992 | |
| 5,239,198 Overmolded semiconductor device having solder ball and edge lead connective structure | 305 | 1992 | |
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| 4,826,787 Method for adhesion of silicon or silicon dioxide plate | 48 | 1987 | |
| 5,051,865 Multi-layer semiconductor device | 54 | 1991 | |
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| 5,422,435 Stacked multi-chip modules and method of manufacturing | 284 | 1992 | |
| 5,495,398 Stacked multi-chip modules and method of manufacturing | 216 | 1995 | |
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| 5,104,820 Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting | 234 | 1991 | |
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| 4,472,875 Method for manufacturing an integrated circuit device | 17 | 1983 | |
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| 4,264,917 Flat package for integrated circuit devices | 129 | 1979 | |
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| 5,331,235 Multi-chip semiconductor package | 81 | 1992 | |
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| 5,426,072 Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate | 235 | 1993 | |
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| 5,675,180 Vertical interconnect process for silicon segments | 74 | 1994 | |
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| 5,387,551 Method of manufacturing flat inductance element | 29 | 1993 | |
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| 5,471,369 Semiconductor device having a plurality of semiconductor chips | 100 | 1994 | |
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| 5,399,898 Multi-chip semiconductor arrangements using flip chip dies | 345 | 1992 | |
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| 5,438,224 Integrated circuit package having a face-to-face IC chip arrangement | 169 | 1993 | |
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| 5,484,959 High density lead-on-package fabrication method and apparatus | 128 | 1992 | |
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| 4,266,334 Manufacture of thinned substrate imagers | 47 | 1979 | |
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| 5,547,906 Methods for producing integrated circuit devices | 88 | 1994 | |
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| 5,483,024 High density semiconductor package | 81 | 1993 | |
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| 5,432,681 Density improvement for planar hybrid wafer scale integration | 23 | 1993 | |
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| 5,019,943 High density chip stack having a zigzag-shaped face which accommodates connections between chips | 92 | 1990 | |
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| 5,266,833 Integrated circuit bus structure | 135 | 1992 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 24, 2013 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 24, 2017 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |