Architecture and interconnect scheme for programmable logic circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 24, 2006
Issued Date -
N/A
app pub date -
Apr 21, 2004
filing date -
Aug 3, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical routing network. Uniformly distributed layers of routing network lines are used to provide connections. Switching networks provide connectability between the routing network lines. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully