Self-aligned source structure of planar DMOS power transistor and its manufacturing methods
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United States of America Patent
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Jan 31, 2006
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N/A
app pub date -
Nov 1, 2004
filing date -
Nov 1, 2004
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Expired
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Abstract
A self-aligned source structure is disclosed by the present invention, in which a p-body diffusion region is formed in an n- epitaxial silicon layer on an n+ silicon substrate through a patterned window; a p+ diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sidewall dielectric spacer being formed over and on a silicon nitride layer; an n+ source diffusion ring is formed in a surface portion of the p-body diffusion region and on an extended portion of the p+ diffusion region through a second self-aligned implantation window formed between the silicon nitride layer and a masking layer surrounded by the first sidewall dielectric spacer; and a self-aligned source contact window is formed on the n+ source diffusion ring surrounded by a second sidewall dielectric spacer and on the p+ diffusion region surrounded by the n+ source diffusion ring.
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