Address generator for fast fourier transform processor
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United States of America Patent
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-
Jan 31, 2006
Grant Date -
Feb 27, 2003
app pub date -
May 7, 2002
filing date -
May 7, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.
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