Semiconductor memory device capable of reducing power consumption during reading and standby
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United States of America Patent
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Feb 14, 2006
Grant Date -
Jan 27, 2005
app pub date -
Jul 21, 2004
filing date -
Jul 24, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The input data at address 0 is '00000000', including many '0's. The data at address 0 is inverted to '11111111'. At the same time, flag information '1' indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many '0's. Therefore, the data of address 3 is inverted, and flag information '1' is written. The input data at addresses 1 and 2 includes more '1's than '0's. Therefore, the data is not inverted, and flag information '0' is written. With regards to the written data, only the data at an address whose flag signal is '1' is inverted again in a reading mode to be eventually read out as a data output signal.
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