Method and apparatus for pipelined joint equalization and decoding for gigabit communications
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United States of America Patent
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Feb 14, 2006
Grant Date -
Jun 27, 2002
app pub date -
Apr 13, 2001
filing date -
Nov 3, 2000
priority date (Note) -
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Abstract
A method and apparatus for the implementation of reduced state sequence estimation is disclosed that uses precomputation (look-ahead) to increase throughput, with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.
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