Method and apparatus for automatically generating hardware from algorithms described in MATLAB
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United States of America Patent
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Feb 14, 2006
Grant Date -
Jan 29, 2004
app pub date -
Jan 26, 2001
filing date -
Jan 26, 2001
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Abstract
Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.
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