Method of making layered superlattice material with improved microstructure

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United States of America Patent

PATENT NO 7001778
APP PUB NO 20040048455A1
SERIAL NO

10415175

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50). In a fourth embodiment, an additional rapid thermal annealing process is performed on a substrate subsequent to the patterning process and prior to the final crystallization annealing process.

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Patent Owner(s)

  • SEIKO EPSON CORPORATION;SYMETRIX CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Joshi, Vikram Colorado Springs, CO 87 3221
Karasawa, Junichi Nagano-ken, JP 85 975

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