Semiconductor memory
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United States of America Patent
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Feb 21, 2006
Grant Date -
Dec 22, 2005
app pub date -
Nov 29, 2004
filing date -
May 20, 2004
priority date (Note) -
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Abstract
A latch signal generator generates a latch signal in synchronization with later one of a timing at which a delayed chip enable signal obtained by delaying a chip enable signal is activated and a transition timing of a clock signal. A latch circuit latches an input signal received by a signal input buffer, in synchronization with the latch signal. By changing the timing the latch signal is generated in accordance with set-up time of the input signal with respect to the clock signal, it is possible to reduce the stand-by current and prevent malfunction of a semiconductor memory caused by improper latch of the input signal.
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